About this paper

Appears in:
Pages: 6415-6421
Publication year: 2013
ISBN: 978-84-616-2661-8
ISSN: 2340-1079

Conference name: 7th International Technology, Education and Development Conference
Dates: 4-5 March, 2013
Location: Valencia, Spain

FAULT SIMULATION TOOLS FOR VLSI FAULT DIAGNOSIS

P. Radoyska, D. Lazarevski, M. Hristova, E. Hristova

Technical University-Sofia (BULGARIA)
Conceptual model and system architecture for self-directed learning was presented in our previous publications. One of most important architectural element is experimental system. This system includes remote labs and simulation environments. We are focused our efforts towards building simulation environment for VLSI circuit diagnosis. The main tools in this environment are: (1) Automatic Test Pattern Generation (ATPG) tool; (2) Diagnostic ATPG (DATPG) tool; (3) Circuit diagnostic tool. These tools have some common modules such as fault simulation and vector generation and as well as some specific modules such as test pattern compactor, diagnosis tree generator and so on. In this paper are presented three fault simulators: concurrent fault simulator for single stuck-at faults; deductive X-fault simulator and event-driven deductive X-fault simulator. X-fault simulators are based on X-fault model, which is used for modeling the multiple faults and Byzantine defects. The two X-fault simulators have been developed in our ambition to optimize performance and reduce simulation time. Here are presented two more tools: X-fault diagnosis tool and measurement simulator. Measurement simulator is developed for verification the diagnostic tools. In the paper are discussed the algorithms and functionality incorporated into the tools as well as obtained results.
@InProceedings{RADOYSKA2013FAU,
author = {Radoyska, P. and Lazarevski, D. and Hristova, M. and Hristova, E.},
title = {FAULT SIMULATION TOOLS FOR VLSI FAULT DIAGNOSIS},
series = {7th International Technology, Education and Development Conference},
booktitle = {INTED2013 Proceedings},
isbn = {978-84-616-2661-8},
issn = {2340-1079},
publisher = {IATED},
location = {Valencia, Spain},
month = {4-5 March, 2013},
year = {2013},
pages = {6415-6421}}
TY - CONF
AU - P. Radoyska AU - D. Lazarevski AU - M. Hristova AU - E. Hristova
TI - FAULT SIMULATION TOOLS FOR VLSI FAULT DIAGNOSIS
SN - 978-84-616-2661-8/2340-1079
PY - 2013
Y1 - 4-5 March, 2013
CI - Valencia, Spain
JO - 7th International Technology, Education and Development Conference
JA - INTED2013 Proceedings
SP - 6415
EP - 6421
ER -
P. Radoyska, D. Lazarevski, M. Hristova, E. Hristova (2013) FAULT SIMULATION TOOLS FOR VLSI FAULT DIAGNOSIS, INTED2013 Proceedings, pp. 6415-6421.
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