About this paper

Appears in:
Pages: 5829-5836
Publication year: 2010
ISBN: 978-84-614-2439-9
ISSN: 2340-1095

Conference name: 3rd International Conference of Education, Research and Innovation
Dates: 15-17 November, 2010
Location: Madrid, Spain


P. Pištek, K. Jelemenská, M. Jurikovič, P. Budinský, R. Marcinčin, T. Palaj, J. Štrba, Ľ. Ubreži

Slovak University of Technology Bratislava, Faculty of Informatics and Information Technologies (SLOVAKIA)
Attracting students’ interest is an issue that is being addressed in all courses. In general, students are more interested in doing practical exercises then learning theory and calculating or designing things on a piece of paper. In courses devoted to logic circuits design it is especially important that the students have the possibility to verify their designs and to experiment with various variations. Some years ago the real logic gates panels were used for this purpose, where students could wire their Boolean functions interconnecting the correct logic gates. These panels were limited in size, the logic gates had limited number of connection ports, and also the types of logic gates were limited to the selected complete set of gates.
With extended use of Electronic Design Automation (EDA) tools the physical verification panels became outdated. However, for learning purpose it would be advantageous to have a tool with certain restrictions e.g. on gates types, number of ports etc. The virtual verification panels can replace the physical ones with much more advantages than just the space savings: various complete sets of logic gates can be available in one panel, the number of gates and their ports can be set up as needed etc.
In the paper, we present the possibility of verification panel virtualization so that it retains some of the useful restrictions. We keep a limited number of logic gates which are available to implement a circuit and the combinations of gates types are restricted to selected complete sets of logic gates. These restrictions force the students to be creative in the design and to try to reach the best space optimization using the minimal number of logic gates. In addition to these limitations, some extensions have been implemented as well i.e. interconnection with Espresso, automated circuit verification, circuit truth table generation, hierarchy support – a logic circuit can be wrapped into a new component further handled as a logic gate.
The proposed tool improves the presentation possibilities in teaching. Teachers can send to students’ a description of a circuit from the initial circuit function specification up to the final circuit. The students have the opportunity to interfere with each of the sent samples, according to their individual needs for better understanding of the actual matter.
In addition to learning part of the software, we put emphasis on creating a testing interface to back-check students' knowledge and gained practical skills. Teacher can create different types of tests with different restrictions. This is a great benefit for students to have the possibility to pass the test in the environment they are already familiar with. After the test has finished, the system automatically evaluates the submitted tests in order to facilitate the teachers work.
The communication between the teacher’s server and the students’ client applications is based on a proprietary communication protocol providing the distribution of tasks as well as automatic collection of results. This solution contributes to the effectiveness and safety of the testing process.
author = {Pištek, P. and Jelemensk{\'{a}}, K. and Jurikovič, M. and Budinský, P. and Marcinčin, R. and Palaj, T. and Štrba, J. and Ubreži, Ľ.},
series = {3rd International Conference of Education, Research and Innovation},
booktitle = {ICERI2010 Proceedings},
isbn = {978-84-614-2439-9},
issn = {2340-1095},
publisher = {IATED},
location = {Madrid, Spain},
month = {15-17 November, 2010},
year = {2010},
pages = {5829-5836}}
AU - P. Pištek AU - K. Jelemenská AU - M. Jurikovič AU - P. Budinský AU - R. Marcinčin AU - T. Palaj AU - J. Štrba AU - Ľ. Ubreži
SN - 978-84-614-2439-9/2340-1095
PY - 2010
Y1 - 15-17 November, 2010
CI - Madrid, Spain
JO - 3rd International Conference of Education, Research and Innovation
JA - ICERI2010 Proceedings
SP - 5829
EP - 5836
ER -
P. Pištek, K. Jelemenská, M. Jurikovič, P. Budinský, R. Marcinčin, T. Palaj, J. Štrba, Ľ. Ubreži (2010) STUDENTS LEARNING IMPROVEMENT USING UNIVERSAL VIRTUAL VERIFICATION PANEL, ICERI2010 Proceedings, pp. 5829-5836.