COOPERATIVE EXPERIENCE TO LEARN THE STANDARD HARDWARE DESCRIPTION LANGUAGE VHDL
University of Almeria (SPAIN)
About this paper:
Appears in: EDULEARN09 Proceedings
Publication year: 2009
Conference name: 1st International Conference on Education and New Learning Technologies
Dates: 6-8 July, 2009
Location: Barcelona ,Spain
Abstract:This work presents the experience of using the cooperative (collaborative) learning (CL) method in the subject of Design and Synthesis of Architectures (DSA). It is an elective subject of the last year of second cycle career of Computer Science Engineering (master degree) of the University of Almería. In this subject, the students must learn the standard hardware description language VHDL (VHSIC-HDL, Very High Speed Integrated Circuit Hardware Description Language) in order to use it to design several architectures. Taking into account that the students have already learned several programming languages, it was quite complicated to keep their attention when teaching the VHDL language using classical passive lecturing way in which students are mere observers that look at and listen to the teacher. For this reason in the last two years the subject has been restructured to an active CL strategy. According to the Johnson model , “cooperative learning is instruction that involves students working in teams to accomplish a common goal, under conditions that include the following elements: (1) positive interdependence, (2) individual accountability, (3) face-to-face promotive interaction, (4) appropriate use of collaborative skills, and (5) group processing”.
The DSA subject has 6 credits: 3 credits of theory (1 session of 2 hours per week) and 3 credits (1 session of 2 hour per week) of laboratory classes. However, the students should work a mean of 8 hours a week in the subject. The theoretical part of the subject basically consists of learning the VHDL language to be able to design all kind of systems, and the FPGAs (Field Programmable Gate Array) platforms where the VHDL design will be implemented. In the laboratory classes the students should use the software tools to design (using VHDL language), simulate, synthesize and route into a FPGA several architectures and complex systems.
Different CL strategies have been carried out.
To learn the VHDL language the Jigsaw structure has been applied using groups of three students. For each theory class, the instructor divides the working material in three distinct parts assigning each one to each team member. Then all the students of each part join together and made themselves expertise in their part, and later on they return to their home teams where each member provide his or her expertise. At the end of the time class the students are tested individually on all of the parts in order to require all students to understand the entire assignment.
To learn about FPGAs, a mix of lecture sessions conducted by the teacher and teamwork sessions has been employed. In addition the students must do some individual homework consisting on reading a paper on FPGAs and VHDL. Later they must summarize it, compare it to another related paper, write a report and give an oral presentation. To evaluate the individual home work of a student, the remaining students must ask several questions after giving the oral presentation and later they must do the critiquing for each other’s report and oral presentation (peer editing). A rubric is used for grading all the evaluated items.
In the practical classes the laboratories and projects may be carried out by teams, though the team grades are adjusted for individual performance including some individual testing.
 Johnson, D. W.; Johnson, R. T.; Smith, K. A. Active Learning: Cooperation in the College Classroom, (2nd ed.); Interaction Book: Edina, MN. 1998.
Keywords: cooperative learning, collaborative learning, education, digital electronics, and.